The present invention generally relates to an integrated circuit (IC) diagnosis technique and, more particularly, to an apparatus and a method for determining the location of an IDDQ defect in an integrated circuit.
Presently, there are several different types of testing methods for detecting faults in integrated circuits. However, one particular method has been widely accepted and successful in the electronics industry. This one particular method comprises a complementary metal oxide semiconductor (CMOS) integrated circuit test method which is known as quiescent power supply current, or IDDQ, testing.
IDDQ testing is attractive because it can achieve high fault coverage with relatively few test patterns, and can detect certain types of unique defects (for example, subtle transistor leakage mechanisms and highly resistive bridges) that logic and functional testing may not detect.
IDDQ testing is based on the observation that certain commonly occurring semiconductor defects, such as bridges or shorts between metal lines, will cause an IC to draw extra supply current, even when the IC is in a “quiescent” state in which all of its intended conduction paths are turned off. Such a defect forms an unintended conduction path between two or more electrically active regions of the IC, and extra current will result (i.e., the defect is “activated”) whenever these regions are at different electrical potentials.
Such a defect, which is detectable by an IDDQ test, will be referred to as an “IDDQ defect” hereafter. Also, the current resulting from a defect will be referred to as “IDDQ defect current”. It should be noted that an IDDQ defect may not be in close physical proximity to the sites in the power and ground networks where the additional current enters and exits the chip. The current arising from a bridge between two signal lines, for example, has its source and sink in the two circuits which drive the bridged lines, either or both of which may be far removed from the location of the actual defect. Hereinafter, for the sake of brevity, any reference to the existence of an IDDQ defect within a particular physical area is intended to include the possibility that the area identified contains only a circuit of which output signal line contains a defect, and that the defect itself may in fact lie outside the area identified.
A single reading is typically obtained by applying a predetermined test pattern to the primary inputs of an IC, allowing the IC to “settle” into a quiescent state, and then measuring the current drawn by the IC in the quiescent state. An IDDQ test normally comprises the application of several such test patterns and measurements. Each pattern places the IC into a different electrical state, thereby increasing the likelihood of activating, and thus of detecting, any IDDQ defects present on the IC.
A semiconductor manufacturer's ability to improve its manufacturing yield depends upon successful physical failure analysis (PFA), in which the root cause of an IC's failure is determined. Central to successful PFA is the ability to determine the physical location of a defect on an IC. Because traditional IDDQ testing measures current at a single point in the IC's power supply, each reading indicates the current drawn by the entire IC. For this reason, traditional IDDQ measurements provide no direct information about the physical location of the defects they detect. A means for determining the location of a defect directly from IDDQ measurements could improve the accuracy and effectiveness of PFA, enabling more rapid improvement of manufacturing yield.
In the absence of such a method, one existing means of locating an IDDQ defect is software diagnosis. Given a logic simulator which can determine the internal electrical state of the IC during each IDDQ measurement, and an indication of which IDDQ measurements “failed” (detected the defect) and which “passed”, IDDQ diagnostic software can determine likely defect sites by identifying internal circuit nodes which, if defective, could explain which patterns pass and fail.
Although test and diagnosis offer unique benefits to IC manufacturers, the effectiveness of IDDQ testing has been generally diminished because of its increasing difficulty of detecting IDDQ defect current in the presence of the overwhelmingly higher background current (e.g., substrate current). Such background current is a very typical phenomenon in modern integrated circuit devices. Even a defect-free integrated circuit draws a certain amount of background current while in a quiescent state because of a normal leakage phenomenon within individual devices (e.g., transistors) within an IC device. As the number of transistors in advanced integrated circuit devices has exponentially grown, the background current arising from their cumulative leakage has increased drastically.
Because the current resulting from an activated IDDQ defect is typically small, the “signal-to-noise” ratio in IDDQ testing (that is, the ratio of defect current to normal background current) has become so low that some IC manufacturers have abandoned IDDQ testing altogether as ineffective for their high-performance IC's. A means of increasing this signal-to-noise ratio would thus not only extend the applicability of IDDQ testing for defect detection, but would improve the capability of software diagnosis by enabling “passing” and “failing” patterns for a given IC to be distinguished more readily.